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1. general description the pca9633 is an i 2 c-bus controlled 4-bit led driver optimized for red/green/blue/amber (rgba) color mixing applications. each led output has its own 8-bit resolution (256 steps) ?xed frequency individual pwm controller that operates at 97 khz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the led to be set to a speci?c brightness value. a ?fth 8-bit resolution (256 steps) group pwm controller has both a ?xed frequency of 190 hz and an adjustable frequency between 24 hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all leds with the same value. each led output can be off, on (no pwm control), set at its individual pwm controller value or at both individual and group pwm controller values. the led output driver is programmed to be either open-drain with a 25 ma current sink capability at 5 v or totem pole with a 25 ma sink, 10 ma source capability at 5 v. the pca9633 operates with a supply voltage range of 2.3 v to 5.5 v and the outputs are 5.5 v tolerant. leds can be directly connected to the led output (up to 25 ma, 5.5 v) or controlled with external drivers and a minimum amount of discrete components for larger current or higher voltage leds. the pca9633 is one of the ?rst led controller devices in a new fast-mode plus (fm+) family. fm+ devices offer higher frequency (up to 1 mhz) and more densely populated bus operation (up to 4000 pf). the active low output enable input pin ( oe) allows asynchronous control of the led outputs and can be used to set all the outputs to a de?ned i 2 c-bus programmable logic state. the oe can also be used to externally pwm the outputs, which is useful when multiple devices need to be dimmed or blinked together using software control. this feature is available for the 16-pin version only. software programmable led group and three sub call i 2 c addresses allow all or de?ned groups of pca9633 devices to respond to a common i 2 c address, allowing for example, all red leds to be turned on or off at the same time or marquee chasing effect, thus minimizing i 2 c-bus commands. the pca9633 is offered with 3 different i 2 c-bus address options: ?xed i 2 c-bus address (8-pin version), 4 different i 2 c-bus addresses from 2 programmable address pins (10-pin version), and 126 different i 2 c-bus addresses from 7 programmable address pins (16-pin version). they are software identical except for the different number of address combinations. the software reset (swrst) call allows the master to perform a reset of the pca9633 through the i 2 c-bus, identical to the power-on reset (por) that initializes the registers to their default state causing the outputs to be set high (led off). this allows an easy and quick way to recon?gure all device registers to the same condition. pca9633 4-bit fm+ i 2 c-bus led driver rev. 05 25 july 2008 product data sheet
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 2 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 2. features n 4 led drivers. each output programmable at: u off u on u programmable led brightness u programmable group dimming/blinking mixed with individual led brightness n 1 mhz fast-mode plus i 2 c-bus interface with 30 ma high drive capability on sda output for driving high capacitive buses n 256-step (8-bit) linear programmable brightness per led output varying from fully off (default) to maximum brightness using a 97 khz pwm signal n 256-step group brightness control allows general dimming (using a 190 hz pwm signal) from fully off to maximum brightness (default) n 256-step group blinking with frequency programmable from 24 hz to 10.73 s and duty cycle from 0 % to 99.6 % n four totem pole outputs (sink 25 ma and source 10 ma at 5 v) with software programmable open-drain led outputs selection (default at totem pole). no input function. n output state change programmable on the acknowledge or the stop command to update outputs byte-by-byte or all at the same time (default to change on stop). n active low output enable ( oe) input pin. led outputs programmable to 1, 0 or high-impedance (default at power-up) when oe is high, thus allowing hardware blinking and dimming of the leds (16-pin version only). n 2 hardware address pins (10-pin version) and 7 hardware address pins (16-pin version) allow respectively up to 4 and 126 devices to be connected to the same i 2 c-bus. no hardware address pins in the 8-pin version. n 4 software programmable i 2 c-bus addresses (one led group call address and three led sub call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for all call so that all the pca9633s on the i 2 c-bus can be addressed at the same time and the second register used for three different addresses so that 1 3 of all devices on the bus can be addressed at the same time in a group). software enable and disable for i 2 c-bus address. n software reset feature (swrst call) allows the device to be reset through the i 2 c-bus n 25 mhz internal oscillator requires no external components n internal power-on reset n noise ?lter on sda/scl inputs n edge rate control on outputs n no glitch on power-up n supports hot insertion n low standby current n operating power supply voltage range of 2.3 v to 5.5 v n 5.5 v tolerant inputs n - 40 c to +85 c operation n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 3 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver n packages offered: so, tssop (msop), hvqfn, hvson 3. applications n rgb or rgba led drivers n led status information n led displays n lcd backlights n keypad backlights for cellular phones or handheld devices 4. ordering information table 1. ordering information type number topside mark package name description version pca9633d16 pca9633 so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 pca9633dp1 9633 tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 pca9633dp2 9633 tssop10 plastic thin shrink small outline package; 10 leads; body width 3 mm sot552-1 pca9633pw pca9633 tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 pca9633bs 9633 hvqfn16 plastic thermal enhanced very thin quad ?at package; no leads; 16 terminals; body 4 4 0.85 mm sot629-1 pca9633tk 9633 hvson8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 3 0.85 mm sot908-1
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 4 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 5. block diagram fig 1. block diagram of pca9633 a0 a1 a2 a3 a4 a5 a6 16-pin version 002aab283 10-pin version i 2 c-bus control input filter pca9633 power-on reset scl sda v dd v ss led s tat e select register pwm register x brightness control grpfreq register grppwm register mux/ control oe (16-pin version only) '0' C permanently off '1' C permanently on v dd ledn 190 hz 24.3 khz 97 khz 25 mhz oscillator
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 5 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 6. pinning information 6.1 pinning fig 2. pin con?guration for tssop8 fig 3. pin con?guration for tssop10 fig 4. pin con?guration for tssop16 fig 5. pin con?guration for so16 fig 6. pin con?guration for hvqfn16 fig 7. pin con?guration for hvson8 pca9633dp1 led0 v dd led1 sda led2 scl led3 v ss 002aab314 1 2 3 4 6 5 8 7 pca9633dp2 led0 v dd led1 sda led2 scl led3 a1 a0 v ss 002aab315 1 2 3 4 5 6 8 7 10 9 pca9633pw 002aab316 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 a0 v dd a1 a6 led0 a5 led1 sda led2 scl led3 a4 a2 oe a3 v ss a0 v dd a1 a6 led0 a5 led1 sda led2 scl led3 a4 a2 oe a3 v ss 002aab313 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 pca9633d16 002aab317 transparent top view led3 a4 led2 scl led1 sda led0 a5 a2 a3 v ss oe a1 a0 v dd a6 4 9 3 10 2 11 1 12 5 6 7 8 16 15 14 13 terminal 1 index area pca9633bs 002aab807 pca9633tk v ss led2 led3 scl led1 sda led0 v dd transparent top view 4 5 3 6 2 7 1 8 terminal 1 index area
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 6 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 6.2 pin description table 2. pin description for tssop8 and hvson8 symbol pin type description led0 1 o led driver 0 led1 2 o led driver 1 led2 3 o led driver 2 led3 4 o led driver 3 v ss 5 power supply supply ground scl 6 i serial clock line sda 7 i/o serial data line v dd 8 power supply supply voltage table 3. pin description for tssop10 symbol pin type description led0 1 o led driver 0 led1 2 o led driver 1 led2 3 o led driver 2 led3 4 o led driver 3 a0 5 i address input 0 v ss 6 power supply supply ground a1 7 i address input 1 scl 8 i serial clock line sda 9 i/o serial data line v dd 10 power supply supply voltage
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 7 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver [1] hvqfn16 package die supply ground is connected to both the v ss pin and the exposed center pad. the v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the pcb in the thermal pad region. table 4. pin description for so16 and tssop16 symbol pin type description a0 1 i address input 0 a1 2 i address input 1 led0 3 o led driver 0 led1 4 o led driver 1 led2 5 o led driver 2 led3 6 o led driver 3 a2 7 i address input 2 a3 8 i address input 3 v ss 9 power supply supply ground oe 10 i active low output enable a4 11 i address input 4 scl 12 i serial clock line sda 13 i/o serial data line a5 14 i address input 5 a6 15 i address input 6 v dd 16 power supply supply voltage table 5. pin description for hvqfn16 symbol pin type description led0 1 o led driver 0 led1 2 o led driver 1 led2 3 o led driver 2 led3 4 o led driver 3 a2 5 i address input 2 a3 6 i address input 3 v ss [1] 7 power supply supply ground oe 8 i active low output enable a4 9 i address input 4 scl 10 i serial clock line sda 11 i/o serial data line a5 12 i address input 5 a6 13 i address input 6 v dd 14 power supply supply voltage a0 15 i address input 0 a1 16 i address input 1
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 8 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7. functional description refer to figure 1 bloc k diag r am of pca9633 . 7.1 device addresses following a start condition, the bus master must output the address of the slave it is accessing. there are a maximum of 128 possible programmable addresses using the 7 hardware address pins. two of these addresses, software reset and led all call, cannot be used because their default power-up state is on, leaving a maximum of 126 addresses. using other reserved addresses, as well as any other subcall address, will reduce the total number of possible addresses even further. 7.1.1 regular i 2 c-bus slave address the i 2 c-bus slave address of the pca9633 is shown in figure 8 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low (10-pin and 16-pin versions). remark: using reserved i 2 c-bus addresses will interfere with other devices, but only if the devices are on the bus and/or the bus will be open to other i 2 c-bus systems at some later date. in a closed system where the designer controls the address assignment these addresses can be used since the pca9633 treats them like any other address. the led all call, software reset and pca9564 or pca9665 slave address (if on the bus) can never be used for individual device addresses. ? pca9633 led all call address (1110 000) and software reset (0000 0110) which are active on start-up ? pca9564 (0000 000) or pca9665 (1110 000) slave address which is active on start-up ? reserved for future use i 2 c-bus addresses (0000 011, 1111 1xx) ? slave devices that use the 10-bit addressing scheme (1111 0xx) ? slave devices that are designed to respond to the general call address (0000 000) ? high-speed mode (hs-mode) master code (0000 1xx). the last bit of the address byte de?nes the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. a. 8-pin version b. 10-pin version c. 16-pin version fig 8. slave address r/w 002aab318 1 1 0 0 0 1 0 fixed slave address r/w 002aab295 1 1 0 0 0 a1 a0 fixed hardware selectable slave address r/w 002aab319 a6 a5 a4 a3 a2 a1 a0 hardware selectable slave address
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 9 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7.1.2 led all call i 2 c-bus address ? default power-up value (allcalladr register): e0h or 1110 000x ? programmable through i 2 c-bus (volatile programming) ? at power-up, led all call i 2 c-bus address is enabled. pca9633 sends an ack when e0h (r/ w = 0) or e1h (r/ w = 1) is sent by the master. see section 7.3.8 led all call i 2 c-b us address , allcalladr for more detail. remark: the default led all call i 2 c-bus address (e0h or 1110 000x) must not be used as a regular i 2 c-bus slave address since this address is enabled at power-up. all the pca9633s on the i 2 c-bus will acknowledge the address if sent by the i 2 c-bus master. 7.1.3 led sub call i 2 c-bus addresses ? 3 different i 2 c-bus addresses can be used ? default power-up values: C subadr1 register: e2h or 1110 001x C subadr2 register: e4h or 1110 010x C subadr3 register: e8h or 1110 100x ? programmable through i 2 c-bus (volatile programming) ? at power-up, sub call i 2 c-bus addresses are disabled. pca9633 does not send an ack when e2h (r/ w = 0) or e3h (r/ w = 1), e4h (r/ w = 0) or e5h (r/ w = 1), or e8h (r/ w = 0) or e9h (r/ w = 1) is sent by the master. see section 7.3.7 i 2 c-b us subaddress 1 to 3, subadrx for more detail. remark: the default led sub call i 2 c-bus addresses may be used as regular i 2 c-bus slave addresses as long as they are disabled. 7.1.4 software reset i 2 c-bus address the address shown in figure 9 is used when a reset of the pca9633 needs to be performed by the master. the software reset address (swrst call) must be used with r/ w = 0. if r/ w = 1, the pca9633 does not acknowledge the swrst. see section 7.6 softw are reset for more detail. remark: the software reset i 2 c-bus address is a reserved address and cannot be used as a regular i 2 c-bus slave address (16-pin version) or as an led all call or led sub call address. fig 9. software reset address 0 002aab416 0 0 0 0 0 1 1 r/w
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 10 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7.2 control register following the successful acknowledgement of the slave address, led all call address or led sub call address, the bus master will send a byte to the pca9633, which will be stored in the control register. the lowest 4 bits are used as a pointer to determine which register will be accessed (d[3:0]). the highest 3 bits are used as auto-increment ?ag and auto-increment options (ai[2:0]). bit 4 is unused and must be programmed with zero (0) for proper device operation. when the auto-increment ?ag is set (ai2 = 1), the four low order bits of the control register are automatically incremented after a read or write. this allows the user to program the registers sequentially. four different types of auto-increment are possible, depending on ai1 and ai0 values. remark: other combinations not shown in t ab le 6 (ai[2:0] = 001, 010, and 011) are reserved and must not be used for proper device operation. ai[2:0] = 000 is used when the same register must be accessed several times during a single i 2 c-bus communication, for example, changes the brightness of a single led. data is overwritten each time the register is accessed during a write operation. ai[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming. ai[2:0] = 101 is used when the four led drivers must be individually programmed with different values during the same i 2 c-bus communication, for example, changing color setting to another color setting. reset state = 80h remark: the control register does not apply to the software reset i 2 c-bus address. fig 10. control register table 6. auto-increment options ai2 ai1 ai0 function 0 0 0 no auto-increment 1 0 0 auto-increment for all registers. d3, d2, d1, d0 roll over to 0000 after the last register (1100) is accessed. 1 0 1 auto-increment for individual brightness registers only. d3, d2, d1, d0 roll over to 0010 after the last register (0101) is accessed. 1 1 0 auto-increment for global control registers only. d3, d2, d1, d0 roll over to 0110 after the last register (0111) is accessed. 1 1 1 auto-increment for individual and global control registers only. d3, d2, d1, d0 roll over to 0010 after the last register (0111) is accessed. 002aab296 ai2 ai1 ai0 0 d3 d2 d1 d0 auto-increment flag register address auto-increment options
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 11 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver ai[2:0] = 110 is used when the led drivers must be globally programmed with different settings during the same i 2 c-bus communication, for example, global brightness or blinking change. ai[2:0] = 111 is used when individual and global changes must be performed during the same i 2 c-bus communication, for example, changing a color and global brightness at the same time. only the 4 least signi?cant bits d[3:0] are affected by the ai[2:0] bits. when the control register is written, the register entry point determined by d[3:0] is the ?rst register that will be addressed (read or write operation), and can be anywhere between 0000 and 1100 (as de?ned in t ab le 7 ). when ai[2] = 1, the auto-increment ?ag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by ai[2:0]. see t ab le 6 for rollover values. for example, if the control register = 1110 1000 (e8h), then the register addressing sequence will be (in hex): 08 ? ? 0c ? 00 ? ? 07 ? 02 ? ? 07 ? 02 ? ? 07 ? 02 ? as long as the master keeps sending or reading data. 7.3 register de?nitions [1] only d[3:0] = 0000 to 1100 are allowed and will be acknowledged. d[3:0] = 1101, 1110, or 1111 are reserved and will not be acknowledged. [2] when writing to the control register, bit 4 must be programmed with logic 0 for proper device operation. table 7. register summary [1] [2] register number (hex) d3 d2 d1 d0 name type function 00h 0 0 0 0 mode1 read/write mode register 1 01h 0 0 0 1 mode2 read/write mode register 2 02h 0 0 1 0 pwm0 read/write brightness control led0 03h 0 0 1 1 pwm1 read/write brightness control led1 04h 0 1 0 0 pwm2 read/write brightness control led2 05h 0 1 0 1 pwm3 read/write brightness control led3 06h 0 1 1 0 grppwm read/write group duty cycle control 07h 0 1 1 1 grpfreq read/write group frequency 08h 1 0 0 0 ledout read/write led output state 09h 1 0 0 1 subadr1 read/write i 2 c-bus subaddress 1 0ah 1 0 1 0 subadr2 read/write i 2 c-bus subaddress 2 0bh 1 0 1 1 subadr3 read/write i 2 c-bus subaddress 3 0ch 1 1 0 0 allcalladr read/write led all call i 2 c-bus address
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 12 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7.3.1 mode register 1, mode1 [1] it takes 500 m s max. for the oscillator to be up and running once sleep bit has been set to logic 0. timings on ledn outputs are not guaranteed if pwmx, grppwm or grpfreq registers are accessed within the 500 m s window. [2] when the oscillator is off (sleep mode) the led outputs cannot be turned on, off or dimmed/blinked. 7.3.2 mode register 2, mode2 table 8. mode1 - mode register 1 (address 00h) bit description legend: * default value. bit symbol access value description 7 ai2 read only 0 register auto-increment disabled 1* register auto-increment enabled 6 ai1 read only 0* auto-increment bi t1=0 1 auto-increment bi t1=1 5 ai0 read only 0* auto-increment bi t0=0 1 auto-increment bi t0=1 4 sleep r/w 0 normal mode [1] . 1* low power mode. oscillator off [2] . 3 sub1 r/w 0* pca9633 does not respond to i 2 c-bus subaddress 1. 1 pca9633 responds to i 2 c-bus subaddress 1. 2 sub2 r/w 0* pca9633 does not respond to i 2 c-bus subaddress 2. 1 pca9633 responds to i 2 c-bus subaddress 2. 1 sub3 r/w 0* pca9633 does not respond to i 2 c-bus subaddress 3. 1 pca9633 responds to i 2 c-bus subaddress 3. 0 allcall r/w 0 pca9633 does not respond to led all call i 2 c-bus address. 1* pca9633 responds to led all call i 2 c-bus address. table 9. mode2 - mode register 2 (address 01h) bit description legend: * default value. bit symbol access value description 7 - read only 0* reserved 6 - read only 0* reserved 5 dmblnk r/w 0* group control = dimming 1 group control = blinking 4 invrt [1] r/w 0* output logic state not inverted. value to use when no external driver used. applicable when oe = 0 for pca9633 16-pin version. 1 output logic state inverted. value to use when external driver used. applicable when oe = 0 for pca9633 16-pin version. 3 och r/w 0* outputs change on stop command. [2] 1 outputs change on ack. 2 outdrv [1] r/w 0 the 4 led outputs are con?gured with an open-drain structure. 1* the 4 led outputs are con?gured with a totem pole structure.
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 13 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver [1] see section 7.7 using the pca9633 with and without e xter nal dr iv ers for more details. normal leds can be driven directly in either mode. some newer leds include integrated zener diodes to limit voltage transients, reduce emi and protect the leds, and these must be driven only in the open-drain mode to prevent overheating the ic. [2] change of the outputs at the stop command allows synchronizing outputs of more than one pca9633. applicable to registers fro m 02h (pwm0) to 08h (ledout) only. [3] see section 7.4 activ e lo w output enab le input for more details. [4] outne[1:0] is only for pca9633 16-pin version. 7.3.3 pwm registers 0 to 3, pwmx individual brightness control registers a 97 khz ?xed frequency signal is used for each output. duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = led output off) to ffh (99.6 % duty cycle = led output at maximum brightness). applicable to led outputs programmed with ldrx = 10 or 11 (ledout register). (1) 7.3.4 group duty cycle control, grppwm when dmblnk bit (mode2 register) is programmed with 0, a 190 hz ?xed frequency signal is superimposed with the 97 khz individual brightness control signal. grppwm is then used as a global brightness control allowing the led outputs to be dimmed with the same value. the value in grpfreq is then a dont care. general brightness for the 4 outputs is controlled through 256 linear steps from 00h (0 % duty cycle = led output off) to ffh (99.6 % duty cycle = maximum brightness). applicable to led outputs programmed with ldrx = 11 (ledout register). 1 to 0 outne[1:0] [3] [4] r/w 00 when oe = 1 (output drivers not enabled), ledn = 0. 01* when oe = 1 (output drivers not enabled): ledn = 1 when outdrv = 1 ledn = high-impedance when outdrv = 0 (same as outne[1:0] = 10) 10 when oe = 1 (output drivers not enabled), ledn = high-impedance. 11 reserved table 9. mode2 - mode register 2 (address 01h) bit description continued legend: * default value. bit symbol access value description table 10. pwm0 to pwm3 - pwm registers 0 to 3 (address 02h to 05h) bit description legend: * default value. address register bit symbol access value description 02h pwm0 7:0 idc0[7:0] r/w 0000 0000* pwm0 individual duty cycle 03h pwm1 7:0 idc1[7:0] r/w 0000 0000* pwm1 individual duty cycle 04h pwm2 7:0 idc2[7:0] r/w 0000 0000* pwm2 individual duty cycle 05h pwm3 7:0 idc3[7:0] r/w 0000 0000* pwm3 individual duty cycle duty cycle idc 7 : 0 [] 256 ------------------------ = table 11. grppwm - group duty cycle control register (address 06h) bit description legend: * default value. address register bit symbol access value description 06h grppwm 7:0 gdc[7:0] r/w 1111 1111 grppwm register
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 14 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver when dmblnk bit is programmed with 1, grppwm and grpfreq registers de?ne a global blinking pattern, where grpfreq contains the blinking period (from 24 hz to 10.73 s) and grppwm the duty cycle (on/off ratio in %). (2) 7.3.5 group frequency, grpfreq grpfreq is used to program the global blinking period when dmblnk bit (mode2 register) is equal to 1. value in this register is a dont care when dmblnk = 0. applicable to led outputs programmed with ldrx = 11 (ledout register). blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 hz) to ffh (10.73 s). (3) 7.3.6 led driver output state, ledout ldrx = 00 led driver x is off (default power-up state). ldrx = 01 led driver x is fully on (individual brightness and group dimming/blinking not controlled). ldrx = 10 led driver x individual brightness can be controlled through its pwmx register. ldrx = 11 led driver x individual brightness and group dimming/blinking can be controlled through its pwmx register and the grppwm registers. duty cycle gdc 7 : 0 [] 256 -------------------------- - = table 12. grpfreq - group frequency register (address 07h) bit description legend: * default value. address register bit symbol access value description 07h grpfreq 7:0 gfrq[7:0] r/w 0000 0000* grpfreq register global blinking period gfrq 7 : 0 [] 1 + 24 --------------------------------------- - in onds sec () = table 13. ledout - led driver output state register (address 08h) bit description legend: * default value. address register bit symbol access value description 08h ledout 7:6 ldr3 r/w 00* led3 output state control 5:4 ldr2 r/w 00* led2 output state control 3:2 ldr1 r/w 00* led1 output state control 1:0 ldr0 r/w 00* led0 output state control
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 15 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7.3.7 i 2 c-bus subaddress 1 to 3, subadrx subaddresses are programmable through the i 2 c-bus. default power-up values are e2h, e4h, e8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding subx bit in mode1 register is equal to 0). once subaddresses have been programmed to their right values, subx bits need to be set to 1 in order to have the device acknowledging these addresses (mode1 register). only the 7 msbs representing the i 2 c-bus subaddress are valid. the lsb in subadrx register is a read-only bit (0). when subx is set to 1, the corresponding i 2 c-bus subaddress can be used during either an i 2 c-bus read or write sequence. 7.3.8 led all call i 2 c-bus address, allcalladr the led all call i 2 c-bus address allows all the pca9633s in the bus to be programmed at the same time (allcall bit in register mode1 must be equal to 1, power-up default state). this address is programmable through the i 2 c-bus and can be used during either an i 2 c-bus read or write sequence. the register address can be programmed as a sub call. only the 7 msbs representing the all call i 2 c-bus address are valid. the lsb in allcalladr register is a read-only bit (0). if allcall bit = 0, the device does not acknowledge the address programmed in register allcalladr. table 14. subadr1 to subadr3 - i 2 c-bus subaddress registers 0 to 3 (address 09h to 0bh) bit description legend: * default value. address register bit symbol access value description 09h subadr1 7:1 a1[7:1] r/w 1110 001* i 2 c-bus subaddress 1 0 a1[0] r only 0* reserved 0ah subadr2 7:1 a2[7:1] r/w 1110 010* i 2 c-bus subaddress 2 0 a2[0] r only 0* reserved 0bh subadr3 7:1 a3[7:1] r/w 1110 100* i 2 c-bus subaddress 3 0 a3[0] r only 0* reserved table 15. allcalladr - led all call i 2 c-bus address register (address 0ch) bit description legend: * default value. address register bit symbol access value description 0ch allcalladr 7:1 ac[7:1] r/w 1110 000* allcall i 2 c-bus address register 0 ac[0] r only 0* reserved
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 16 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7.4 active low output enable input the active low output enable ( oe) pin, allows to enable or disable all the led outputs at the same time. this control signal is only available for the 16-pin version and does not apply to the 8-pin or 10-pin versions. ? when a low level is applied to oe pin, all the led outputs are enabled and follow the output state de?ned in the ledout register with the polarity de?ned by invrt bit (mode2 register). ? when a high level is applied to oe pin, all the led outputs are programmed to the value that is de?ned by outne[1:0] in the mode2 register. the oe pin can be used as a synchronization signal to switch on/off several pca9633 devices at the same time. this requires an external clock reference that provides blinking period and the duty cycle. the oe pin can also be used as an external dimming control signal. the frequency of the external clock must be high enough not to be seen by the human eye, and the duty cycle value determines the brightness of the leds. remark: do not use oe as an external blinking control signal when internal global blinking is selected (dmblnk = 1, mode2 register) since it will result in an unde?ned blinking pattern. do not use oe as an external dimming control signal when internal global dimming is selected (dmblnk = 0, mode2 register) since it will result in an unde?ned dimming pattern. 7.5 power-on reset when power is applied to v dd , an internal power-on reset holds the pca9633 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pca9633 registers and i 2 c-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. thereafter, v dd must be lowered below 0.2 v to reset the device. table 16. led outputs when oe=1 outne1 outne0 led outputs 000 0 1 1 if outdrv = 1, high-impedance if outdrv = 0 1 0 high-impedance 1 1 reserved
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 17 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7.6 software reset the software reset call (swrst call) allows all the devices in the i 2 c-bus to be reset to the power-up state value through a speci?c formatted i 2 c-bus command. to be performed correctly, it implies that the i 2 c-bus is functional and that there is no device hanging the bus. the swrst call function is de?ned as the following: 1. a start command is sent by the i 2 c-bus master. 2. the reserved swrst i 2 c-bus address 0000 011 with the r/ w bit set to 0 (write) is sent by the i 2 c-bus master. 3. the pca9633 device(s) acknowledge(s) after seeing the swrst call address 0000 0110 (06h) only. if the r/ w bit is set to 1 (read), no acknowledge is returned to the i 2 c-bus master. 4. once the swrst call address has been sent and acknowledged, the master sends 2 bytes with 2 speci?c values (swrst data byte 1 and byte 2): a. byte 1 = a5h: the pca9633 acknowledges this value only. if byte 1 is not equal to a5h, the pca9633 does not acknowledge it. b. byte 2 = 5ah: the pca9633 acknowledges this value only. if byte 2 is not equal to 5ah, then the pca9633 does not acknowledge it. if more than 2 bytes of data are sent, the pca9633 does not acknowledge any more. 5. once the right 2 bytes (swrst data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a stop command to end the swrst call: the pca9633 then resets to the default value (power-up value) and is ready to be addressed again within the speci?ed bus free time (t buf ). the i 2 c-bus master must interpret a non-acknowledge from the pca9633 (at any time) as a swrst call abort. the pca9633 does not initiate a reset of its registers. this happens only when the format of the swrst call sequence is not correct.
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 18 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7.7 using the pca9633 with and without external drivers the pca9633 led output drivers are 5.5 v only tolerant and can sink up to 25 ma at 5 v. if the device needs to drive leds to a higher voltage and/or higher current, use of an external driver is required. ? invrt bit (mode2 register) can be used to keep the led pwm control ?rmware the same (pwmx and grppwm values directly calculated from their respective formulas and the led output state determined by ledout register value) independently of the type of external driver. this bit allows led output polarity inversion/non-inversion only when oe=0. ? outdrv bit (mode2 register) allows minimizing the amount of external components required to control the external driver (n-type or p-type device). [1] oe applies to 16-pin version only. when oe = 1, led output state is controlled only by outne[1:0] bits (mode2 register). [2] correct con?guration when leds directly connected to the ledn outputs (connection to v dd through current limiting resistor). [3] optimum con?guration when external n-type (npn, nmos) driver used. [4] optimum con?guration when external p-type (pnp, pmos) driver used. table 17. use of invrt and outdrv based on connection to the ledn outputs when oe=0 [1] invrt outdrv direct connection to ledn external n-type driver external p-type driver firmware external pull-up resistor firmware external pull-up resistor firmware external pull-up resistor 0 0 formulas and led output state values apply [2] led current limiting r [2] formulas and led output state values inverted required formulas and led output state values apply required 0 1 formulas and led output state values apply [2] led current limiting r [2] formulas and led output state values inverted not required formulas and led output state values apply [4] not required [4] 1 0 formulas and led output state values inverted led current limiting r formulas and led output state values apply required formulas and led output state values inverted required 1 1 formulas and led output state values inverted led current limiting r formulas and led output state values apply [3] not required [3] formulas and led output state values inverted not required
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 19 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver [1] oe applies to 16-pin version only. when oe = 1, led output state is controlled only by outne[1:0] bits (mode2 register). [2] external pull-up or led current limiting resistor connects ledn to v dd . table 18. output transistors based on ledout registers, invrt and outdrv bits when oe = 0 [1] ledout invrt outdrv upper transistor (v dd to ledn) lower transistor (ledn to v ss ) ledn state 00 led driver off 0 0 off off high-z [2] 0 1 on off v dd 1 0 off on v ss 1 1 off on v ss 01 led driver on 0 0 off on v ss 0 1 off on v ss 1 0 off off high-z [2] 1 1 on off v dd 10 individual brightness control 0 0 off individual pwm (non-inverted) v ss or high-z [2] = pwmx value 0 1 individual pwm (non-inverted) individual pwm (non-inverted) v ss or v dd = pwmx value 1 0 off individual pwm (inverted) high-z [2] or v ss = 1 - pwmx value 1 1 individual pwm (inverted) individual pwm (inverted) v dd or v ss = 1 - pwmx value 11 individual + group dimming/blinking 0 0 off individual + group pwm (non-inverted) v ss or high-z [2] = pwmx/grppwm values 0 1 individual pwm (non-inverted) individual pwm (non-inverted) v ss or v dd = pwmx/grppwm values 1 0 off individual + group pwm (inverted) high-z [2] or v ss = (1 - pwmx) or (1 - grppwm) values 1 1 individual pwm (inverted) individual pwm (inverted) v dd or v ss =(1 - pwmx) or (1 - grppwm) values
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 20 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 7.8 individual brightness control with group dimming/blinking a 97 khz ?xed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each led. on top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 led outputs): ? a lower 190 hz ?xed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control. ? a programmable frequency signal from 24 hz to 1 10.73 hz (8 bits, 256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control. minimum pulse width for ledn brightness control is 40 ns. minimum pulse width for group dimming is 20.48 m s. when m = 1 (grppwm register value), the resulting ledn brightness control + group dimming signal will have 2 pulses of the led brightness control signal (pulse width = n 40 ns, with n de?ned in pwmx register). this resulting brightness + group dimming signal above shows a resulting control signal with m = 4 (8 pulses). fig 11. brightness + group dimming signals 123456789101112 507 508 509 510 511 512 1234567891011 brightness control signal (ledn) m 256 2 40 ns with m = (0 to 255) (grppwm register) n 40 ns with n = (0 to 255) (pwmx register) 256 40 ns = 10.24 m s (97.6 khz) 12345678 12345678 group dimming signal resulting brightness + group dimming signal 256 2 256 40 ns = 5.24 ms (190.7 hz) 002aab417
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 21 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 8. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 12 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 13 ). 8.2 system con?guration a device generating a message is a transmitter; a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 14 ). fig 12. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 13. de?nition of start and stop conditions mba608 sda scl p stop condition sda scl s start condition
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 22 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 8.3 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 14. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 15. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 23 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 9. bus transactions (1) 16-pin version only. (2) see t ab le 7 for register de?nition. fig 16. write to a speci?c register a5 a4 a3 a2 a1 a0 0 a s a6 slave address (1) start condition r/w acknowledge from slave 002aab418 data for register d3, d2, d1, d0 (2) x x 0 d3 d2 d1 d0 x control register auto-increment flag auto-increment options a acknowledge from slave a acknowledge from slave p stop condition (1) 16-pin version only. fig 17. write to all registers using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address (1) start condition r/w acknowledge from slave 002aab419 mode1 register 0 0 0 0 0 0 0 1 control register auto-increment on auto-increment on all registers a acknowledge from slave a acknowledge from slave p stop condition (cont.) (cont.) mode1 register selection mode2 register a acknowledge from slave subadr3 register a acknowledge from slave allcalladr register a acknowledge from slave
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 24 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver (1) 16-pin version only. fig 18. multiple writes to individual brightness registers only using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address (1) start condition r/w acknowledge from slave 002aab420 pwm0 register 0 1 0 0 0 1 0 1 control register auto-increment on increment on individual brightness registers only a acknowledge from slave a acknowledge from slave p stop condition (cont.) (cont.) pwm0 register selection pwm1 register a acknowledge from slave pwm2 register a acknowledge from slave pwm3 register a acknowledge from slave pwm0 register a acknowledge from slave pwmx register a acknowledge from slave (1) 16-pin version only. fig 19. read all registers using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address (1) start condition r/w acknowledge from slave 002aab423 0 0 0 0 0 0 0 1 control register auto-increment on auto-increment on all registers a acknowledge from slave (cont.) (cont.) mode1 register selection data from mode1 register a acknowledge from master sr restart condition a5 a4 a3 a2 a1 a0 1 a a6 slave address (1) r/w acknowledge from slave data from mode2 register a acknowledge from master data from pwm0 a acknowledge from master data from allcalladr register a acknowledge from master data from mode1 register a acknowledge from master (cont.) (cont.) data from last read byte a not acknowledge from master p stop condition
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 25 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver (1) 10-pin version is used for this ?gure. four pca9633dp2s are used and the same sequence (a) (above) is sent to each of them. a[1:0] = 00 to 11. (2) allcall bit in mode1 register is equal to 1 for this example. (3) och bit in mode2 register is equal to 1 for this example. fig 20. led all call i 2 c-bus address programming and led all call sequence example 1 0 0 0 a1 a0 0 a s 1 slave address (1) start condition r/w acknowledge from slave 002aab424 x x 0 1 1 0 0 x control register auto-increment on a acknowledge from slave allcalladr register selection 0 1 0 1 0 1 x 1 new led all call i 2 c address (2) p stop condition a acknowledge from slave 0 1 0 1 0 1 0 a s 1 led all call i 2 c address start condition r/w acknowledge from the 4 devices x x 0 1 0 0 0 x control register a acknowledge from the 4 devices ledout register selection 1 0 1 0 1 0 1 0 ledout register (led fully on) p stop condition a acknowledge from the 4 devices the 16 leds are on at the acknowledge (3) sequence (a) sequence (b) fig 21. software reset (swrst) call sequence 002aab425 0 0 0 0 1 1 0 a s 0 swrst call i 2 c address start condition r/w acknowledge from slave(s) 0 1 0 0 1 0 1 1 swrst data byte 1 = a5h a acknowledge from slave(s) 1 0 1 1 0 1 0 0 swrst data byte 2 = 5ah p pca9633(s) is(are) reset. registers are set to default power-up values. a acknowledge from slave(s)
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 26 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 10. application design-in information question 1: what kind of edge rate control is there on the outputs? ? the typical edge rates depend on the output con?guration, supply voltage, and the applied load. the outputs can be con?gured as either open-drain nmos or totem pole outputs. if the customer is using the part to directly drive leds, they should be using it in an open-drain nmos, if they are concerned about the maximum iss and ground bounce. the edge rate control was designed primarily to slow down the turn-on of the output device; it turns off rather quickly (~1.5 ns). in simulation, the typical turn-on time for the open-drain nmos was ~14 ns (v dd = 3.6 v; c l = 50 pf; r pu = 500 w ). question 2: is ground bounce possible? ? ground bounce is a possibility, especially if all 16 outputs are changed at full current (25 ma each). there is a fair amount of decoupling capacitance on chip (~50 pf), which is intended to suppress some of the ground bounce. the customer will need to determine if additional decoupling capacitance externally placed as close as physically possible to the device is required. i 2 c-bus address = 0010 101x. all of the 4 ledn outputs con?gurable as either open-drain or totem pole. mixing of con?gurations is not possible. (1) oe requires pull-up resistor if control signal from the master is open-drain. fig 22. typical application pca9633 led0 led1 sda scl oe v dd = 2.5 v, 3.3 v or 5.0 v i 2 c-bus/smbus master 002aab286 sda scl 10 k w oe 10 k w led2 led3 a0 a1 a2 v dd a3 a4 a5 a6 v ss 5 v 10 k w (1) 12 v
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 27 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver question 3: can i really sink 400 ma through the single ground pin on the package and will this cause any ground bounce problem due to the pwm of the leds? ? yes, you can sink 400 ma through a single ground pin on the package . although the package only has one ground pin, there are two ground pads on the die itself connected to this one pin. although some ground bounce is likely, it will not disrupt the operation of the part and would be reduced by the external decoupling capacitance. question 4: i cant turn the leds on or off, but their registers are set properly. why? ? check the mode register 1 bit 4 sleep setting. the value needs to be 0 so that the osc is turn on. if the osc is turned off, the leds cannot be turned on or off and also cant be dimmed or blinked. question 5: im using leds with integrated zener diodes and the ic is getting very hot. why? ? the ic outputs can be set to either open-drain or push-pull and default to push-pull outputs. in this application with the zener diodes, they need to be set to open-drain since in the push-pull architecture there is a low resistance path to gnd through the zener and this is causing the ic to overheat. the pca9632/33/34/35 ics all power-up in the push-pull output mode and with the logic state high, so one of the ?rst things that need to be done is to set the outputs to open-drain. 11. limiting values table 19. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.0 v v i/o voltage on an input/output pin v ss - 0.5 5.5 v i o(ledn) output current on pin ledn - 25 ma i ss ground supply current - 100 ma p tot total power dissipation - 400 mw t stg storage temperature - 65 +150 c t amb ambient temperature operating - 40 +85 c
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 28 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 12. static characteristics table 20. static characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 5.5 v i dd supply current operating mode; no load; f scl = 1 mhz v dd = 2.3 v - 2.5 10 ma v dd = 3.3 v - 2.5 10 ma v dd = 5.5 v - 2.5 10 ma i stb standby current no load; f scl = 0 hz; i/o = inputs; v i =v dd v dd = 2.3 v - 2.3 11 m a v dd = 3.3 v - 2.9 12 m a v dd = 5.5 v - 3.8 15.5 m a v por power-on reset voltage no load; v i =v dd or v ss [1] - 1.70 2.0 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i ol low-level output current v ol = 0.4 v; v dd = 2.3 v 20 - - ma v ol = 0.4 v; v dd = 5.0 v 30 - - ma i l leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss - 6 10 pf led driver outputs i ol low-level output current v ol = 0.5 v; v dd = 2.3 v [2] 12 - - ma v ol = 0.5 v; v dd = 3.0 v [2] 17 - - ma v ol = 0.5 v; v dd = 4.5 v [2] 25 - - ma i ol(tot) total low-level output current v ol = 0.5 v; v dd = 4.5 v [2] - - 100 ma i oh high-level output current open-drain; v oh =v dd - 50 - +50 m a v oh high-level output voltage i oh = - 10 ma; v dd = 2.3 v 1.6 - - v i oh = - 10 ma; v dd = 3.0 v 2.3 - - v i oh = - 10 ma; v dd = 4.5 v 4.0 - - v c o output capacitance - 2.5 5 pf oe input v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2 - 5.5 v i li input leakage current - 1- +1 m a c i input capacitance - 3.7 5 pf
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 29 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver [1] v dd must be lowered to 0.2 v in order to reset part. [2] each bit must be limited to a maximum of 25 ma and the total package limited to 100 ma due to internal busing limits. 13. dynamic characteristics [1] minimum scl clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either sda or s cl is held low for a minimum of 25 ms. disable bus time-out feature for dc operation. [2] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [3] t vd;dat = minimum time for sda data out to be valid following scl low. [4] c b = total capacitance of one bus line in pf. address inputs v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i li input leakage current - 1- +1 m a c i input capacitance - 3.7 5 pf table 20. static characteristics continued v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 21. dynamic characteristics symbol parameter conditions standard- mode i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus unit min max min max min max f scl scl clock frequency [1] 0 100 0 400 0 1000 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - m s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - m s t hd;dat data hold time 0 - 0 - 0 - ns t vd;ack data valid acknowledge time [2] 0.3 3.45 0.1 0.9 0.05 0.45 m s t vd;dat data valid time [3] 0.3 3.45 0.1 0.9 0.05 0.45 m s t su;dat data set-up time 250 - 100 - 50 - ns t low low period of the scl clock 4.7 - 1.3 - 0.5 - m s t high high period of the scl clock 4.0 - 0.6 - 0.26 - m s t f fall time of both sda and scl signals [5] [6] - 300 20 + 0.1c b [4] 300 - 120 ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [4] 300 - 120 ns t sp pulse width of spikes that must be suppressed by the input ?lter [7] - 50 - 50 - 50 ns
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 30 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver [5] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the unde?ned region of scls falling edge. [6] the maximum t f for the sda and scl bus lines is speci?ed at 300 ns. the maximum fall time (t f ) for the sda output stage is speci?ed at 250 ns. this allows series protection resistors to be connected between the sda and the scl pins and the sda/scl bus lines witho ut exceeding the maximum speci?ed t f . [7] input ?lters on the sda and scl inputs suppress noise spikes less than 50 ns. fig 23. de?nition of timing t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 rise and fall times refer to v il and v ih . fig 24. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab285 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 1 (d1) bit 0 (d0) 1 / f scl t r t vd;dat acknowledge (a) stop condition (p)
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 31 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 14. test information r l = load resistor for ledn. r l for sda and scl > 1 k w (3 ma or less current). c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 25. test circuitry for switching times pulse generator v o c l 50 pf r l 500 w 002aab880 r t v i v dd dut v dd open v ss
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 32 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 15. package outline fig 26. package outline sot109-1 (so16) x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 33 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver fig 27. package outline sot505-1 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.70 0.35 6 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot505-1 99-04-09 03-02-18 w m b p d z e 0.25 14 8 5 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 1.1 pin 1 index
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 34 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver fig 28. package outline sot552-1 (tssop10) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.15 0.23 0.15 3.1 2.9 3.1 2.9 0.5 5.0 4.8 0.67 0.34 6 0 0.1 0.1 0.1 0.95 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot552-1 99-07-29 03-02-18 w m b p d z e 0.25 15 10 6 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop10: plastic thin shrink small outline package; 10 leads; body width 3 mm sot552-1 1.1 pin 1 index
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 35 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver fig 29. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 36 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver fig 30. package outline sot629-1 (hvqfn16) terminal 1 index area 0.65 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.1 3.9 d h 2.25 1.95 y 1 4.1 3.9 2.25 1.95 e 1 1.95 e 2 1.95 0.38 0.23 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot629-1 mo-220 - - - - - - 0.75 0.50 l 0.1 v 0.05 w 0 2.5 5 mm scale sot629-1 hvqfn16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 58 16 13 12 9 4 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 37 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver fig 31. package outline sot908-1 (hvson8) 0.5 0.2 1 0.05 0.00 a 1 e h b unit d (1) y e 1.5 e 1 references outline version european projection issue date iec jedec jeita mm 3.1 2.9 cd h 1.65 1.35 y 1 3.1 2.9 2.25 1.95 0.3 0.2 0.05 0.1 dimensions (mm are the original dimensions) sot908-1 mo-229 e (1) 0.5 0.3 l 0.1 v 0.05 w sot908-1 hvson8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm a (1) max. 05-09-26 05-10-05 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. x terminal 1 index area b a d e detail x a a 1 c c y c y 1 exposed tie bar (4 ) exposed tie bar (4 ) b terminal 1 index area e 1 e a c b v m c w m e h d h l 14 5 8 0 1 2 mm scale
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 38 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 16. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 39 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities 17.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 32 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 22 and 23 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 32 . table 22. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 23. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 40 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 18. abbreviations msl: moisture sensitivity level fig 32. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 24. abbreviations acronym description cdm charged-device model dut device under test emi electromagnetic interference esd electrostatic discharge hbm human body model i 2 c-bus inter-integrated circuit bus lcd liquid crystal display led light emitting diode lsb least signi?cant bit mm machine model msb most signi?cant bit nmos negative-channel metal-oxide semiconductor pcb printed-circuit board pmos positive-channel metal-oxide semiconductor pwm pulse width modulation rgb red/green/blue rgba red/green/blue/amber smbus system management bus
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 41 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 19. revision history table 25. revision history document id release date data sheet status change notice supersedes pca9633_5 20080725 product data sheet - pca9633_4 modi?cations: ? section 2 f eatures : C 9 th bullet item: changed up to 4 and 126 pca9633 devices to up to 4 and 126 devices C deleted (old) 12 th bullet item ? section 7.1.1 regular i 2 c-b us sla v e address : remark re-written; added (new) 1 st and 2 nd bullet items ? figure 21 softw are reset (swrst) call sequence : C changed byt e 1 = 0xa5 to byt e 1 = a5h C changed byt e 2 = 0x5a to byt e 2 = 5ah ? figure 25 t est circuitr y f or s witching times : changed gnd to v ss pca9633_4 20080304 product data sheet - pca9633_3 pca9633_3 20061220 product data sheet - pca9633_2 pca9633_2 20061114 product data sheet - pca9633_1 pca9633_1 (9397 750 14614) 20060123 product data sheet - -
pca9633_5 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 05 25 july 2008 42 of 43 nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 20.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 20.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 20.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca9633 4-bit fm+ i 2 c-bus led driver ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 25 july 2008 document identifier: pca9633_5 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . . 8 7.1 device addresses . . . . . . . . . . . . . . . . . . . . . . . 8 7.1.1 regular i 2 c-bus slave address . . . . . . . . . . . . . 8 7.1.2 led all call i 2 c-bus address . . . . . . . . . . . . . . 9 7.1.3 led sub call i 2 c-bus addresses . . . . . . . . . . . 9 7.1.4 software reset i 2 c-bus address . . . . . . . . . . . 9 7.2 control register . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3 register de?nitions . . . . . . . . . . . . . . . . . . . . . 11 7.3.1 mode register 1, mode1 . . . . . . . . . . . . . . . . 12 7.3.2 mode register 2, mode2 . . . . . . . . . . . . . . . . 12 7.3.3 pwm registers 0 to 3, pwmx individual brightness control registers . . . . . . . . . . . . . . 13 7.3.4 group duty cycle control, grppwm . . . . . . . 13 7.3.5 group frequency, grpfreq . . . . . . . . . . . . . 14 7.3.6 led driver output state, ledout . . . . . . . . . 14 7.3.7 i 2 c-bus subaddress 1 to 3, subadrx . . . . . . 15 7.3.8 led all call i 2 c-bus address, allcalladr. 15 7.4 active low output enable input . . . . . . . . . . . 16 7.5 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 software reset . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7 using the pca9633 with and without external drivers . . . . . . . . . . . . . . . . . . . . . . . . 18 7.8 individual brightness control with group dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 20 8 characteristics of the i 2 c-bus. . . . . . . . . . . . . 21 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1.1 start and stop conditions . . . . . . . . . . . . . 21 8.2 system con?guration . . . . . . . . . . . . . . . . . . . 21 8.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 23 10 application design-in information . . . . . . . . . 26 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 12 static characteristics. . . . . . . . . . . . . . . . . . . . 28 13 dynamic characteristics . . . . . . . . . . . . . . . . . 29 14 test information . . . . . . . . . . . . . . . . . . . . . . . . 31 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 16 handling information. . . . . . . . . . . . . . . . . . . . 38 17 soldering of smd packages . . . . . . . . . . . . . . 38 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 38 17.2 wave and re?ow soldering . . . . . . . . . . . . . . . 38 17.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 38 17.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 39 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 41 20 legal information . . . . . . . . . . . . . . . . . . . . . . 42 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 42 20.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 20.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 42 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 21 contact information . . . . . . . . . . . . . . . . . . . . 42 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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